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Content Provider | IET Digital Library |
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Author | Chuxiong, Wu Haifeng, Shi |
Abstract | Fibre channel (FC) provides the high-speed and low-latency communication between the end systems, widely used in data storage, aerospace applications and large electronic equipment including radar systems. Excellent in error detection and easy to be implemented in hardware, cyclic redundancy check (CRC) is an important error detection method widely used in network data transmission. This study introduces a design and development of parallel CRC algorithm for the hardware implementation on FPGA to meet the specifications for FC. The algorithm can process 128-bit parallel data in a block by broken it into four 32-bit data and calculate their CRC, respectively, based on the linear feedback shift register, simplifying the calculation process and reducing resource consumption. |
Starting Page | 7827 |
Ending Page | 7830 |
Page Count | 4 |
Volume Number | 2019 |
e-ISSN | 20513305 |
Issue Number | Issue 21, Nov (2019) |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/joe/2019/21 |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/joe.2019.0727 |
Journal | The Journal of Engineering |
Publisher | The Institution of Engineering and Technology |
Publisher Date | 2019-08-13 |
Access Restriction | Open |
Rights License | Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) |
Subject Keyword | 128-bit Parallel Data 32-bit Data Aerospace Application Cyclic Redundancy Check Cyclic Redundancy Check Codes Data Storage Electronic Equipment Including Radar System End System Error Detection Fibre Channel Field Programmable Gate Array FPGA Hardware Implementation Important Error Detection Method Logic And Switching Circuit Logic Circuit Low-latency Communication Network Data Transmission Parallel CRC Algorithm Shift Registers |
Content Type | Text |
Resource Type | Article |
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