NDLI: FPGA-based reconfigurable matrix inversion implementation for inverse filtering of multi-channel SAR imaging

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FPGA-based reconfigurable matrix inversion implementation for inverse filtering of multi-channel SAR imaging

Content Provider	IET Digital Library
Author	Li, Hui Xing Feng, Yang Kai Hu, Shan Qing Li, Bing Yi Xie, Yi Zhuang Wu, Meng Chao
Abstract	In multi-channel synthetic aperture radar (SAR), the azimuth non-uniform sampling tends to result in a large number of virtual point targets, which are not expected. Inverse filter algorithm provides a new idea for solving this problem. This way can be abstracted as a matrix inversion in essence, which becomes the key factor that affects the real-time and accuracy of multi-channel pre-processing. This study presents the implementation of matrix inversion method on field programmable gate array (FPGA), based on lower and upper triangular matrix (LU) decomposition algorithm. In this process, the efficient parallelism of FPGA and the rich floating-point intellectual property (IP) cores are fully utilised to speed up the process of inverting the matrix with a data type of 32-bit single-precision floating-point. In this design, the parallelism of the algorithm was fully considered and a hierarchical iterative processing strategy was adopted to realise the reconfigurable storage and computing unit both. At the same time, in order to achieve the balance of resources and efficiency, a reusable structure was proposed also, using the pipeline technology and appropriate data scheduling. Finally, Modelsim platform is used to observe the simulation results, and the performance can be detected combined with MATLAB platform. At last, the computational accuracy is up to 10 − 7 , and the speedup ratio can reach about 1.461 × 10 3 .
Starting Page	8027
Ending Page	8031
Page Count	5
Volume Number	2019
e-ISSN	20513305
Issue Number	Issue 21, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/joe/2019/21
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/joe.2019.0748
Journal	The Journal of Engineering
Publisher	The Institution of Engineering and Technology
Publisher Date	2019-08-13
Access Restriction	Open
Rights License	Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Subject Keyword	Azimuthal Nonuniform Sampling Result Computer Vision And Image Processing Technique Computing Unit Data Scheduling Digital Arithmetic Method Field Programmable Gate Array Filtering Method in Signal Processing Filtering Theory Floating Point Arithmetic Floating-point IP Cores FPGA-based Reconfigurable Matrix Inversion Implementation Hierarchical Iterative Processing Strategy Image Sampling Inverse Filter Algorithm Iterative Method Linear Algebra Logic And Switching Circuit Logic Circuit LU Decomposition Algorithm Matrix Inversion Matrix Inversion Method Microprocessor Chips Microprocessors And Microcomputer Modelim Platform Multichannel Preprocessing Multichannel SAR Imaging Multichannel Synthetic Aperture Radar Multiprocessing System Numerical Analysis Optical, Image And Video Signal Processing Parallel Architecture Pipeline Processing Pipeline Technology Processor Scheduling Radar Equipment Radar Imaging Reconfigurable Architectures Reconfigurable Storage Resource Allocation Resource Balancing Reusable Structure Single-precision Floating-point Data Type Synthetic Aperture Radar System And Application Virtual Point
Content Type	Text
Resource Type	Article

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