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Parallel CRC Computation in FPGAs (1996)
| Content Provider | CiteSeerX |
|---|---|
| Author | Braun, Michael Friedrich, Jörg Grün, Thomas Lembert, Josef |
| Description | . This paper presents how to compute n-bit CRC checksums on FPGAs in parallel. For this task, a specialized logic minimization strategy is outlined. It achieves significantly better results than standard logic optimizers. For n 96, CRC designs with an n-bit I/O interface are poorly routable. However, for smaller I/O interfaces even a 128-bit CRC can be implemented. 1 Introduction Using CRC style checksums (cyclic redundancy check) [4] is a simple and powerful method for detecting transmission errors in data communication systems. It is well suited for high speed serial transmission equipment, because it can be implemented on chip with a shift register and some XOR gates at nearly no cost. However, for some purposes it is necessary to implement a CRC calculation off the serial transmission chip, e.g., if additional error detection is required [2, 3]. Then, chip-to-chip delay and achievable clock rates prohibit a bit-serial CRC implementation, and a parallel calculation has to be used.... |
| File Format | |
| Language | English |
| Publisher Date | 1996-01-01 |
| Publisher Institution | in Workshop on Field Programmable Logic and Applications |
| Access Restriction | Open |
| Subject Keyword | Serial Transmission Chip N-bit Crc Checksum Powerful Method 128-bit Crc Parallel Crc Computation Chip-to-chip Delay Shift Register Specialized Logic Minimization Strategy Standard Logic Optimizers Parallel Calculation High Speed Serial Transmission Equipment Cyclic Redundancy Check Xor Gate Data Communication System Crc Calculation Introduction Using Crc Style Checksum Bit-serial Crc Implementation Transmission Error Additional Error Detection Achievable Clock Rate |
| Content Type | Text |
| Resource Type | Article |
