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| Content Provider | IET Digital Library |
|---|---|
| Author | Casu, M. R. Yadav, M. K. Zamboni, M. |
| Abstract | A new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers. Instead of turning-off the buffers completely, a buffer portion is kept turned-on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade-offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalty. |
| Starting Page | 1438 |
| Ending Page | 1440 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 49 |
| e-ISSN | 1350911X |
| Issue Number | Issue 23, Nov (2013) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/23 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2013.3225 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Buffer Leakage Power Reduction Buffer Utilisation Nonuniformity CMOS Integrated Circuit CMOS Technology Electrical Fault Network Packet Network-on-chip Network-on-chip Buffers Power-gating Technique Size 45 Nm Video Application Benchmarks |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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