NDLI: Area- and power-efficient DC–DC converter with on-chip compensation

Content Provider	IET Digital Library
Author	Liu, Pang Jung Chang, Yi Hsiang
Abstract	A dual-path capacitor multiplier (DPCM) technique is proposed for on-chip frequency compensation. The DPCM uses two currents to charge and discharge a compensation capacitor concurrently. Consequently, the equivalent capacitance is amplified dramatically with slight increase in silicon area and power. Thanks to the DPCM, the transient response of the DC–DC converter has improved significantly because of the small compensation capacitor. Experimental results demonstrate converter stability and transient response. The transient recovery time of a 450 mA step load change is <30 μs. With the proposed technique, the compensation capacitor is shrunk significantly and adding the compensation resistor would have helped in improving transient response.
Starting Page	1157
Ending Page	1158
Page Count	2
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 16, Jul (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/16
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.0459
Journal	Electronics Letters
Publisher Date	2014-07-23
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Area-efficient DC-DC Converter Capacitor Circuit Stability Compensation Compensation Capacitor Compensation Resistor Current 450 MA DC-DC Power Converter DPCM Technique Dual-path Capacitor Multiplier Technique Elemental Semiconductor Equivalent Capacitance Logic Circuit Multiplying Circuit On-chip Frequency Compensation Power Electronics Power Supply Power-efficient DC-DC Converter Resistor Silicon Stability Supervisory Circuit Transient Response
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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