NDLI: Optimization of sense amplifier energy recovery flip-flop

Content Provider	IEEE Xplore Digital Library
Author	Brindha, B. Bhaaskaran, V.S.K. Vinoth, C. Kavinilavu, V. Sakthikumaran, S.
Copyright Year	2011
Description	Author affiliation: SSN College of Engineering, Kalavakkam, Rajiv Gandhi Salai, (Off) Chennai, Tamil Nadu, India (Brindha, B.; Bhaaskaran, V.S.K.; Vinoth, C.; Kavinilavu, V.; Sakthikumaran, S.)
Abstract	This paper presents a novel sense amplifier energy recovery flip-flop which realizes better area efficiency and less power consumption compared to conventional sense amplifier energy recovery flip-flop. This is achieved by replacing the storage element of conventional sense amplifier energy recovery flip-flop with 2N-2N2P structure which works on the principle of adiabatic logic. The resulting flip-flop outweighs the conventional flip-flop with 22% reduction in power consumption and 10% reduction in silicon area. Reduced power consumption against various energy recovery flip flops such as DCCER (Differential Conditional Capturing Energy Recovery) flip-flop, SCCER (Single-Ended Conditional Capturing Energy Recovery) flip-flop, SDER (Static Differential Energy Recovery) flip-flop is also proved. The simulations have been carried out at a frequency of 100MHz across a voltage range from 2.2V to 3.3V.
Starting Page	317
Ending Page	319
File Size	258571
Page Count	3
File Format	PDF
ISBN	9781424486786
e-ISBN	9781424486793
DOI	10.1109/ICECTECH.2011.5941614
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-08
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Strontium Power demand Latches Logic gates Energy Recovery Logic Low power VLSI Circuits Transistors Flip-Flops Flip-flops Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Low-Power Double Edge-Triggered Flip-Flop Circuit Design

Power optimization for VLSI circuits and systems

A novel methodology for flip-flop optimization and characterization in NOC design space

A high-speed sense-amplifier based flip-flop

Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity

Low Power Subthreshold D Flip Flop

Dual-edge triggered sense-amplifier flip-flop for Low Power systems

A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family

A technique for low power testing of VLSI chips

Optimization of sense amplifier energy recovery flip-flop

Similar Documents

Low-Power Double Edge-Triggered Flip-Flop Circuit Design

Power optimization for VLSI circuits and systems

A novel methodology for flip-flop optimization and characterization in NOC design space

A high-speed sense-amplifier based flip-flop

Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity

Low Power Subthreshold D Flip Flop

Dual-edge triggered sense-amplifier flip-flop for Low Power systems

A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family

A technique for low power testing of VLSI chips

Optimization of sense amplifier energy recovery flip-flop