NDLI: Digital in-situ biasing technique

Content Provider	IET Digital Library
Author	Hsu, Chun Wei Kinget, Peter R.
Abstract	A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (CMOS) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced CMOS process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm CMOS process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.
Starting Page	897
Ending Page	899
Page Count	3
ISSN	00135194
Volume Number	51
e-ISSN	1350911X
Issue Number	Issue 12, Jun (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/51/12
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.0649
Journal	Electronics Letters
Publisher Date	2015-05-18
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Analogue CMFB Analogue Function Analogue Interfaces Circuit Feedback CMOS Integrated Circuit CMOS Logic Circuit CMOS Process CMOS Technology Common-mode Voltage Differential Amplifier Differential Amplifiers Digital Biasing Circuit Digital Biasing Scheme Digital Circuit Design, Modelling And Testing Digital CMFB Digital Common-mode Feedback Circuit Digital In-situ Biasing Solution Digital In-situ Biasing Technique Intradie Variations Logic And Switching Circuit Logic Circuit Logic Design Method Nanoscale Complementary Metal-oxide Semiconductor Size 65 Nm Time-based Successive Approximation Conversion Ultra-compact Digital Logic
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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