NDLI: Design of ultra-low power AES encryption cores with silicon demonstration in SOTB CMOS process

Content Provider	IET Digital Library
Author	Hoang, V. P. Dao, V. L. Pham, C. K.
Abstract	The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.
Starting Page	1512
Ending Page	1514
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 23, Nov (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/23
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2017.2151
Journal	Electronics Letters
Publisher Date	2017-10-05
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Advanced Encryption Standard Clock Gating Technique Clocks CMOS Integrated Circuit Cores Cryptography Digital Circuit Elemental Semiconductor Inductors And Transformer Integrated Circuit Design Internet of Things System Layout Low Power Electronics Modelling And Testing Semiconductor Integrated Circuit Design Silicon Size 65 Nm SOTB CMOS Process Ultralow Power 2-Sbox AES Encryption Core Wireless Network
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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