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| Content Provider | IET Digital Library |
|---|---|
| Author | Meng, F. Li, K. Thomson, D. J. Wilson, P. Reed, G. T. |
| Abstract | The effect of optimising the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes is investigated, demonstrated in a 28 nm high-K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used. |
| Starting Page | 486 |
| Ending Page | 488 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 54 |
| e-ISSN | 1350911X |
| Issue Number | Issue 8, Apr (2018) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/54/8 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2017.4453 |
| Journal | Electronics Letters |
| Publisher Date | 2018-03-08 |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Advanced Layout Technique Analogue Circuit Design Benchmark Design Circuit Optimisation CMOS Analogue Integrated Circuit CMOS Integrated Circuit Deep Sub-micron Processes Figure of Merit High-k Dielectric Thin Film High-K-metal Gate CMOS Technology Process High-speed Analogue Circuit High-speed Integrated Circuit HKMG CMOS Process Integrated Circuit Layout Layout Modelling Modelling And Testing Oscillator Semiconductor Integrated Circuit Design Size 28 Nm Size 440 Nm Testing Transistor Circuit Transistor Finger Optimization Effect |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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