NDLI: Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

Content Provider	IET Digital Library
Author	Shang, Xinchao Shan, Weiwei Xiang, Yiming Wan, Liang Fan, Ao
Abstract	Variation in on-chip power supply continues to be a major challenge to limit circuit performance. To mitigate the impact of high-frequency voltage droop, a novel all-digital adaptive clock system is proposed. The adaptive clock system is composed of a droop detector and an adaptive clock generator, which directly stretch the clock period when the circuit suffers from the supply voltage droop. The droop detector circuit detects the VDD droop and the digital adaptive clock generator circuit selects the stretched clock to prevent timing-margin failures. The response time for droop detection and clock stretch can be as fast as one cycle. The whole scheme is used on a test circuit under SMIC 40nm CMOS process with a layout area of 900um*1100um. Postlayout simulation results demonstrate power reductions are 7% at 1.1V and 15% at 0.7V for a 10% VDD droop, respectively.
Starting Page	503
Ending Page	507
Page Count	5
ISSN	10224653
Volume Number	28
e-ISSN	20755597
Issue Number	Issue 3, May (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/cje/28/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/cje.2019.02.009
Journal	Chinese Journal of Electronics
Publisher Date	2019-05-01
Access Restriction	Open
Rights Holder	© Chinese Institute of Electronics
Subject Keyword	All-digital Adaptive Clock System Circuit For Digital Computers Circuit Performance Clock Period Clock Stretch Clocks CMOS Digital Integrated Circuit CMOS Integrated Circuit Digital Adaptive Clock Generator Circuit Digital Circuit Digital Circuit Design, Modelling And Testing Droop Detection Droop Detector Circuit Failure Analysis Fast Reaction Adaptive Clocking System High-frequency Voltage Droop Integrated Circuit Design Layout Low Power Electronics Modelling And Testing On-chip Power Supply Post Layout Simulation Power Electronics Power Reductions Power Supply Power Supply Circuit Semiconductor Integrated Circuit Design Size 40.0 Nm SMIC CMOS Process Stretched Clock Supervisory Circuit Supply Voltage Droop Test Circuit Timing-margin Failure Prevention Voltage 0.7 V Voltage 1.1 V Voltage Droop Tolerance
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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