NDLI: Autonomous high-speed serial link power management depending on required link performance for HMC

Content Provider	IET Digital Library
Author	Jeon, D. I. Chung, K. S.
Abstract	Many studies on 3D-stacked dynamic RAMs (DRAMs) have been conducted to overcome the shortcomings of conventional DRAM. The hybrid memory cube (HMC) is one of the most promising 3D-stacked DRAMs, thanks to its high bandwidth and expandable structure. However, a high-speed serial link that interfaces the CPU and HMC consumes significant power, primarily because of the high overhead incurred in synchronising its clock. Although the link provides low-power modes, managing them is very difficult because of their long mode transition times. An autonomous power management method for the high-speed link is proposed. The proposed method determines the optimal number of active links while satisfying the required link performance. Simulations demonstrate that the proposed method reduces link power consumption by an average of 63.06% with a performance degradation of only 1.36%. Therefore, this proposed autonomous link power management is an outstanding option for low-power HMC-based systems.
Starting Page	932
Ending Page	934
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 15, Jul (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/15
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.0997
Journal	Electronics Letters
Publisher Date	2018-06-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	3D-stacked DRAMs 3D-stacked Dynamic RAMs Active Link Autonomous High-speed Serial Link Power Management Clock Synchronisation Conventional DRAM CPU DRAM Chips Electrical/electronic Equipment Energy Utilisation High-speed Link Hybrid Memory Cube Link Performance Link Power Consumption Reduction Long Mode Transition Times Low-power HMC-based System Low-power Mode Memory Circuit Power Aware Computing Power Consumption Semiconductor Storage Synchronisation Three-dimensional Integrated Circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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