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| Content Provider | IET Digital Library |
|---|---|
| Author | Shen, Changsheng |
| Abstract | A background bit-weight calibration in pipelined successive approximation register ADC is proposed. By exploiting the conversion results of the first stage to determine the injection of the dithered signal and introducing two extra capacitors into the first stage to reduce the range of first-stage residue, a robust and totally background calibration is implemented. According to the simulation, the signal-to-noise and distortion ratio and spurious free dynamic range are improved from 66.3 to 73.3 dB and 78.4 to 85.1 dB, respectively, after calibration. |
| Starting Page | 15 |
| Ending Page | 17 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 56 |
| e-ISSN | 1350911X |
| Issue Number | Issue 1, Jan (2020) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/56/1 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2019.2636 |
| Journal | Electronics Letters |
| Publisher Date | 2019-10-25 |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | A/D And D/A Convertor Analogue-Digital Conversion Background Bit-weight Calibration Calibration Capacitor First-stage Residue Pipelined Successive Approximation Register ADC Signal-to-noise And Distortion Ratio Spurious Free Dynamic Range |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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