NDLI: Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

Content Provider	IET Digital Library
Author	Dokania, Vishesh Islam, Aminul
Abstract	Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.
Starting Page	204
Ending Page	212
Page Count	9
ISSN	1751858X
Volume Number	9
e-ISSN	17518598
Issue Number	Issue 3, May (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/9/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2014.0167
Journal	IET Circuits, Devices & Systems
Publisher Date	2015-05-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adder Aggressive Technology Circuit-level Design Technique CMOS Integrated Circuit CMOS Logic Circuit Complementary Metal-oxide Semiconductor Full Adder Cell Complementary Metal-oxide Semiconductor Predictive Technology Model Digital Circuit Digital Circuit Design, Modelling And Testing FA Cell Full Adder Cell Design Metric Inverting Low Voltage Schmitt Trigger Sub-circuits Logic And Switching Circuit Logic Circuit Logic Design Method Logic Element Logic Gate Monte Carlo Simulation Method Near-threshold Region Power Consumption Power-delay Product Process Voltage And Temperature Variation Impact Mitigation PVT Variations Size 16 Nm SPICE Environment Trigger Circuit Ultra-deep Sub-micron Technology Node Voltage Scaling
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reliability and performance of optimised Schmitt trigger gates

Digital in-situ biasing technique

A 62 mV 0.13 $mu$ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

Design of normalised and simplified FAs in quantum-dot cellular automata

High-performance full adder architecture in quantum-dot cellular automata

Design of non-restoring divider in quantum-dot cellular automata technology

Design of high-speed, low-power, and area-efficient FIR filters

Low-power high-speed full adder for portable electronic applications

Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology

Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

Similar Documents

Reliability and performance of optimised Schmitt trigger gates

Digital in-situ biasing technique

A 62 mV 0.13 $mu$ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

Design of normalised and simplified FAs in quantum-dot cellular automata

High-performance full adder architecture in quantum-dot cellular automata

Design of non-restoring divider in quantum-dot cellular automata technology

Design of high-speed, low-power, and area-efficient FIR filters

Low-power high-speed full adder for portable electronic applications

Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology

Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells