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| Content Provider | IET Digital Library |
|---|---|
| Author | Tung, C. K. Shieh, S. H. Cheng, C. H. |
| Abstract | A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60–73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to provide a 20.4–21.2% power saving, a 12.3–67.0% delay time reduction and a 35–102% reduction in power delay product compared with the referenced FAs. In short, an LPHS-FA is presented in a concise form as a high-performance FA in practical applications. |
| Starting Page | 1063 |
| Ending Page | 1064 |
| Page Count | 2 |
| ISSN | 00135194 |
| Volume Number | 49 |
| e-ISSN | 1350911X |
| Issue Number | Issue 17, Aug (2013) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/17 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2013.0893 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Adder Circuit Complexity Reduction CMOS Digital Integrated Circuit CMOS Integrated Circuit Delay Time Reduction HSPICE Simulations Insulated Gate Field Effect Transistors Logic And Switching Circuit Logic Circuit Low Power Electronics Low-power High-speed Full Adder LPHS-FA Metal Oxide Semiconductor Field Effect Transistors MOSFET Portable Electronic Application Power Delay Product Size 0.18 Mum TSMC CMOS Process Technology |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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