NDLI: Benchmarking of Novel Contact Architectures on Silicon and Germanium

Content Provider	IEEE Xplore Digital Library
Author	Ahmed, K. Chopra, S. Agrawal, A. Datta, S.
Copyright Year	2012
Abstract	Novel contact architectures to n-Silicon (n-Si) and to n-Germanium (n-Ge) were benchmarked for the first time against the state-of-the-art contact architecture to n-Si. It was found that although the recently reported contact architectures to n-Ge exhibit markedly improved performance, more work must be done to match state-of the-art NiSi/n-Si contact architecture in terms of current-carrying capability. With the continued scaling of contact length in accordance with Moore's law, the interface resistance between metal and semiconductor has become a critical area of focus to achieve the required targets for lower external series resistance (Fig. 1, Fig. 2). Prior studies have shown effective pathways to lower the interface resistance for p-MOSFETs, like the use of narrow bandgap Silicon-Germanium (SiGe) compounds in Source/Drain (S/D) regions in silicon channel transistors. In addition, the use of a Germanium channel device provides inherent benefit of Fermi-level pinning near the valence band for contacts to p-Ge S/D. Alternative contact architectures are now being sought to improve the interface contact resistance to n-Si (for Silicon channel CMOS) and to n-Ge (for Germanium channel CMOS) by reducing the Schottky Barrier Height (SBH) between metal and n-type S/D semiconductors. In this work, a metric which is based on current density (J) at given semiconductor doping density (ND) was found to be most suitable for benchmarking contact architectures of widely varying maturities. Metal-Insulator-Semiconductor (MIS) contact architecture, in contrast to current Metal-Semiconductor (MS) architecture, has been proposed to reduce SBH by unpinning the Fermi level [1-2]. There is a concern, however, that the insertion of a high bandgap oxide results in large tunnel resistance and would offset the positive effect of Fermi level unpinning. It is therefore necessary to benchmark the current-carrying capability of the MIS contact architectures on both n-Si and n-Ge with respect to state-of-the-art solution. Since J depends exponentially on ND, we propose to use J versus ND as a way to benchmark different MIS contact architectures. The reference NiSi/n-Si and PtSi/n-Si current density data was obtained from [3], and J vs. ND data was fitted to an analytical model [4]. A SBH of 0.55eV provided best fit (Fig. 4), consistent with numerical QM analysis done on the same data set [5]. It is also consistent with values extracted on nanoscale contacts for NiPtSi/n-Si contact architecture with heavily doped S/D semiconductor (31020 cm-3) [6]. In one study, a TaN/LaO/n-Si (MIS) contact stack [2] is benchmarked against the NiSi/n-Si reference system in Fig. 5. The TaN/LaO/n-Si contact stack provides a very promising result. The benefit demonstrated at low ND, however, needs to be demonstrated at ND 31020 cm-3. Various contact architectures to n-Ge are also benchmarked using J vs. ND plot in Fig. 6. Data was taken from [1, 7-10]. When an insulator is inserted between the metal and n-Ge, J is attenuated due to the insulator energy barrier. For example see TiO2/n-Ge, AlO/n-Ge, MgO/n-Ge data points which are lower than the reference line. This leads us to conclude that the MIS contact architecture on n-Ge currently underperforms state-of-the-art NiSi/n-Si system.
Starting Page	1
Ending Page	2
File Size	516567
Page Count	2
File Format	PDF
ISBN	9781457718649
e-ISBN	9781457718656
e-ISBN	9781457718632
DOI	10.1109/ISTDM.2012.6222471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistance Neodymium Benchmark testing Germanium Contact resistance CMOS integrated circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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