NDLI: Timing correlation between clock & data strobe with dynamic rank switching in DDR3 RDIMMs

Content Provider	IEEE Xplore Digital Library
Author	Lingambudi, Anil Wright, Kenneth Zevin, William Sethuraman, Saravanan Saurabh, Abhijit Pullelli, Sivaram Vijay, Siddharth
Copyright Year	2014
Description	Author affiliation: Enterprise Systems & Technology Group, IBM, Austin, TX, USA (Wright, Kenneth) \|\| Enterprise Systems & Technology Group, IBM, Bangalore, IN, India (Lingambudi, Anil; Sethuraman, Saravanan; Saurabh, Abhijit; Pullelli, Sivaram; Vijay, Siddharth) \|\| Enterprise Systems & Technology Group, IBM, RTP, NC, USA (Zevin, William)
Abstract	Memory plays a significant role in successful operations of modern day servers. DDR3 memory has been around for a while and the next generation is almost available. There are lots of challenges which still exist and are not fully uncovered with the DDR3 based ISRDIMMs and discussed in this paper is a unique problem faced during the server memory characterization of ISRDIMMs. Issues were unearthed in timing relationship between the Clock and WR DQS in a multi-Rank DIMM and experiments were conducted to find a suitable solution. The proposed solution uses a Built-In-Self-Test engine to toggle the phase rotator attached to a particular bit to overcome the zero timing margin issues. Experiments were conducted with single and multi-Rank DIMMs, sequential & random DATA pattern and with different addressing schemes to root cause the problem and ensure the proposed solution works fine in all cases.
Starting Page	1
Ending Page	5
File Size	728016
Page Count	5
File Format	PDF
e-ISBN	9781479953646
DOI	10.1109/INDICON.2014.7030663
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	phase rotator timing margins Random access memory Switches Registers signal integrity analysis Synchronization multi rank DDR3 memory Data strobe RDIMM Delays Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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