NDLI: Exploiting hardware abstraction for hybrid parallel computing framework

Content Provider	IEEE Xplore Digital Library
Author	Hongyuan Ding Miaoqing Huang
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA (Hongyuan Ding; Miaoqing Huang)
Abstract	Dedicated hardware modules on Field-Programmable Gate Arrays (FPGAs) are applied to achieve significant performance improvement over the software implementations. However, even in a simple system-on-chip (SoC) design on FPGA, hardware accelerators are managed explicitly by writing hardware/software interfaces. Programmers have to go through massive details to control and communicate with hardware accelerators, not to mention complicated functions to achieve memory allocation and hardware reuse. Besides, designing hardware accelerators still lacks productivity and flexibility. Promising data-level parallel applications can be accelerated by using recent parallel programming models. In this work, we extend software threads to hardware threads. By implementing a hybrid parallel computing framework the parallel applications are supported through the scheduling and reusing of the threads. Programmers can create software threads in an embedded OS environment without managing hardware details. Hardware manager takes over software threads and manage hardware resources in terms of reallocation and isolation. Experimental results demonstrate that hardware threads can achieve up to 10 times speedup over software implementation. The relationships between the length of scheduling time slices, and the performance and the response time are carefully evaluated. Besides, as the number of threads increases, the system demonstrates a good scalability.
Starting Page	1
Ending Page	7
File Size	469031
Page Count	7
File Format	PDF
e-ISBN	9781467394062
DOI	10.1109/ReConFig.2015.7393305
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruction sets Linux Computational modeling Hardware Kernel Message systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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