NDLI: Private circuits II versus fault injection attacks

Content Provider	IEEE Xplore Digital Library
Author	Rakotomalala, H. Xuan Thuy Ngo Najm, Z. Danger, J.-L. Guilley, S.
Copyright Year	2015
Description	Author affiliation: Inst. MINES-TELECOM, TELECOM ParisTech, Paris, France (Rakotomalala, H.; Xuan Thuy Ngo; Najm, Z.) \|\| Secure-IC S.A.S., Cesson-Sevigne, France (Danger, J.-L.; Guilley, S.)
Abstract	Cryptographic implementations are subject to physical attacks. Private circuits II is a proven protection against a strong attacker, able to read and write on a finite number of chosen internal nodes. In practice, side-channel analyses and fault injections are less accurate: typically, classical injection techniques (clock and power glitches, electromagnetic pulses, etc.) can be reproducible, but they do not allow to choose the targeted nodes (the situation is different for software dual-rail with precharge logic, such as [1], [2], where (0, 1) /spl harr/ (1, 0) bitflips are easier to achieve, since the computation is fully sequentialized [3]). So, a priori, private circuits II should be a secure protection against such classical fault injection attacks. In this paper, we provide the first implementation of private circuits II in FPGA, secure against read and/or reset of one internal wire chosen by the attacker. Our implementation is a manually coded netlist which instantiates LUT6_2 (with dual outputs, as required for private circuits II). Our design is a SIMON block cipher programmed in a Spartan 6 Xilinx FPGA. It features a throughput of 142 Mbit/s. We perform a security analysis, and notice that some exploitable ciphertexts can be outputted despite the countermeasure. Our analysis reveals that correlated faults exist because LUT6_2 outputs are produced almost simultaneously. In particular, the critical path actually consists in a dual-rail pair, which is consistently faulted together. If this pair is late with respect to the clock rising edge, then the previous value can be latched instead of the new one. Such fault behaves like a toggle ((01)2 becomes (10)2 or vice-versa) of licit values. They propagate to the ciphertext which becomes by the same token susceptible to a differential fault attack. Nonetheless, we emphasize that such faults require a steady fault injection setup: otherwise, multiple critical paths are violated, resulting in non-exploitable (fully zeroized) ciphertexts.
Starting Page	1
Ending Page	9
File Size	2078530
Page Count	9
File Format	PDF
e-ISBN	9781467394062
DOI	10.1109/ReConFig.2015.7393338
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ciphers Fault injection attack Wires Correlated faults on dual LUT6 2 outputs Logic gates Fault effect analysis with ChipScope Private circuits II Circuit faults Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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