NDLI: Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes

Content Provider	IEEE Xplore Digital Library
Author	Ruizy, M. Suttery, G. Lopez-Buedo, S. Ramosy, J. Lopez de Vergara, J.E. Aracil, J.
Copyright Year	2015
Description	Author affiliation: NAUDIT HPCN, Madrid, Spain (Lopez-Buedo, S.; Lopez de Vergara, J.E.; Aracil, J.) \|\| High-Performance Comput. & Networking Res. Group, Univ. Autonoma de Madrid, Cantoblanco, Spain (Ruizy, M.; Suttery, G.; Ramosy, J.)
Abstract	Nowadays, 10 Gb/s networks are becoming more and more widespread. Consequently, there is an increasing need for testing equipment for those networks, to measure parameters such as throughput, delay, jitter, packet loss rate, etc. Network testing equipment can be either active or passive, depending on whether it injects traffic or simply monitors packets in network links. In this paper we focus on active network probes, particularly those which are based on injection of packet trains. This type of probes have the advantage of causing little interference with existing network traffic, even though they are quite effective to measure several network parameters such as throughput or delay. Here, we take advantage of the open source NetFPGA project to implement a 10 GbE active monitoring probe based on the packet-train technique. In order to reduce development time, we used NetFPGA's OSNT (Open Source Network Tester) monitor project as a starting point, and we also used high-level synthesis tools (namely, Vivado-HLS) to implement the IP core in charge of computing network parameters. Such two design strategies turned out to be very effective both in terms of coding productivity and accuracy of measurements. Actually, the quality of measurements was found to be much better than that obtained with software solutions running on commodity servers, though the development effort was not significantly higher, thanks to the use of open source platforms and high-level synthesis techniques.
Starting Page	1
Ending Page	6
File Size	327224
Page Count	6
File Format	PDF
e-ISBN	9781467394062
DOI	10.1109/ReConFig.2015.7393325
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	NetFPGA High-Level Synthesis Open Source Throughput Generators Loss measurement Network Delay Link Throughput Packet-Train Active Network Probe Hardware Delays Probes Monitoring 10 Gb/s Ethernet
Content Type	Text
Resource Type	Article

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