NDLI: Very low resource table-based FPGA evaluation of elementary functions

Content Provider	IEEE Xplore Digital Library
Author	Neto, H.C. Vestias, M.P.
Copyright Year	2013
Description	Author affiliation: INESC-ID/IST/ULisboa, Lisbon, Portugal (Neto, H.C.) \|\| INESC-ID/ISEL/IPL, Lisbon, Portugal (Vestias, M.P.)
Abstract	This paper analyzes the FPGA implementation of polynomial-based function evaluation specifically considering the embedded block RAMs and multiplier-adders available in today's technologies. The computation of the reciprocal, square root and inverse square root functions using first and second order polynomial approximations is discussed, in particular. In each case, the most appropriate sizes for the interpolation intervals are selected according to the maximum polynomial approximation errors. Upper-bounds for the truncation errors are formally derived in order to find the most appropriate sizes for the polynomial coefficients and fixed-point operands. The bit-sizes of the polynomial coefficients are optimized so that all the required values fit in only one 36Kbit BRAM. Further, the word lengths and the number of fractional bits of the operands are adjusted so that the fixed-point multiplications and additions can be implemented with the 17×24 unsigned multipliers and 48-bit adders available in the FPGA DSP blocks. The experimental results confirm that a straightforward implementation of the function evaluator using one BRAM and two DSP blocks can provide more than single-precision. Additionally, an implementation with one BRAM and three DSPs can provide a precision of 28-bits, which is more than adequate to generate the seed for a double-precision operator using one additional Newton-Raphson iteration.
Starting Page	1
Ending Page	6
File Size	223878
Page Count	6
File Format	PDF
e-ISBN	9781479920792
DOI	10.1109/ReConFig.2013.6732336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Upper bound Computer architecture Digital signal processing Polynomials Approximation methods Finite wordlength effects Field programmable gate arrays
Content Type	Text
Resource Type	Article

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