NDLI: Design of low area-overhead ring oscillator PUF with large challenge space

Content Provider	IEEE Xplore Digital Library
Author	Sahoo, D.P. Mukhopadhyay, D. Chakraborty, R.S.
Copyright Year	2013
Description	Author affiliation: eSE, IIT Kharagpur, Kharagpur, India (Sahoo, D.P.; Mukhopadhyay, D.; Chakraborty, R.S.)
Abstract	Exorbitantly high resource-overhead is an important limiting factor for designing a Ring Oscillator Physically Unclonable Function (ROPUF) with large challenge-space. This work presents a design approach for large ROPUF with much lesser resource than that required for classical ROPUF design. It exploits small ROPUFs as design building blocks. Quality of the proposed scheme has been validated by the design of 60-bit ROPUF on Altera FPGA (Field Programmable Gate Array) that is physically infeasible according to previously proposed direct design principles. The hardware resource required for the 60-bit proposed ROPUF design is lesser than that for 10-bit classic ROPUF. In addition, implementation of 60-bit proposed ROPUF shows 47% uniqueness and 91 % reliability on average.
Starting Page	1
Ending Page	6
File Size	1076590
Page Count	6
File Format	PDF
e-ISBN	9781479920792
DOI	10.1109/ReConFig.2013.6732277
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ring oscillators challenge-response pair Systematics process variation ring oscillator PUF Silicon Delays Reliability Arbiter PUF Field programmable gate arrays physically unclonable junction
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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