NDLI: A VLSI architecture for the QR decomposition based on the MCGR algorithm

Content Provider	IEEE Xplore Digital Library
Author	Cervantes-Lozano, P. Gonzalez-Perez, L.F. Garcia-Garcia, A.D.
Copyright Year	2013
Description	Author affiliation: ITESM, Guadalajara, Mexico (Gonzalez-Perez, L.F.) \|\| ITESM, Mexico City, Mexico (Cervantes-Lozano, P.; Garcia-Garcia, A.D.)
Abstract	This article presents a VLSI (Very Large Scale of Integration) architecture for the QR decomposition (QRD) based on the Modified Complex Givens Rotations (MCGR) algorithm. Being the QRD a fundamental matrix-computation tool for factorizing matrices (matrix decomposition), its vast set of applications is extended to solve several engineering problems in many areas. For example, in the context of Spatial-Multiplexing Multiple-Input Multiple-Output (SM-MIMO) systems, signal processing tasks oriented to decoding purposes are alleviated by the use of pre-processing modules based on a QRD kernel. Under this topic, several techniques are available for implementing the QRD. The classical techniques used for these purposes are: the Modified Gram-Schmidt Orthogonalization (MGS), the Householder Transformations (Hd-t), and indeed the MCGR. The MCGR algorithm is chosen due to its best trade-off between complexity and numerical precision, as well as offering suitability for VLSI architectures. Synthesis results for this VLSI architecture over FPGA (Field Programmable Gate Array) devices are reported. The flexible and scalable design for the MCGR algorithm incorporates CORDIC (Coordinate Rotation Digital Computer) processors and systolic arrays within its configuration, improving hardware complexity and temporal performance, and evidencing competitive aspects against other related solutions.
Starting Page	1
Ending Page	6
File Size	382812
Page Count	6
File Format	PDF
e-ISBN	9781479920792
DOI	10.1109/ReConFig.2013.6732267
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MIMO systems Program processors Modified Complex Givens Rotations QR decomposition Very large scale integration systolic arrays VLSI architectures Complexity theory Arrays Matrix decomposition Indexes CORDIC processors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in