NDLI: Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Content Provider	IEEE Xplore Digital Library
Author	Bai Yu Alawad, M. Riera, M. Mingjie Lin
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA (Bai Yu; Alawad, M.; Riera, M.; Mingjie Lin)
Abstract	Being “memory-centric”, the single-chip distributed logic-memory (DLM) architecture can significantly improve the overall performance and energy efficiency of many memory-intensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis. We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmic centric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to [1] (A2). To make our comparison fair, in all three architectures, the data path remains the same while local memory architecture differs. For each of ten benchmark applications from SPEC2006 and MiBench [2], we break down the performance benefit of using A3 into two parts: the portion due to stochastic local memory partitioning and the portion due to the dynamic graph-based memory arbitration. All experiments have been conducted with a Virtex-5 (XCV5LX155T2) FPGA. On average, our experimental results show that our proposed A3 architecture outperforms A2 and A1 by 34% and 250%, respectively. Within the performance improvement of A3 over A2, more than 70% improvement comes from the hardware graph-based memory scheduling.
Starting Page	1
Ending Page	8
File Size	256261
Page Count	8
File Format	PDF
e-ISBN	9781479920792
DOI	10.1109/ReConFig.2013.6732300
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heuristic algorithms Random access memory Computer architecture Hardware Partitioning algorithms Timing Field programmable gate arrays
Content Type	Text
Resource Type	Article

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