NDLI: The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture

Content Provider	IEEE Xplore Digital Library
Author	Farooq, U. Marrakchi, Z. Mrabet, H. Mehrez, H.
Copyright Year	2008
Description	Author affiliation: LIP6, Univ. Pierre et Marie Curie, Paris (Farooq, U.; Marrakchi, Z.; Mrabet, H.; Mehrez, H.)
Abstract	In this paper we present the effect of lookup table (LUT)size (no of inputs to a LUT) and cluster size (no of LUTs per cluster) on the area and critical path of a tree based FPGA architecture (MFPGA). For this purpose we have designed a flow that places and routes a set of bench mark circuits on different tree based architectures with varying lookup table (lookup table size varies from 3 to 7) and cluster sizes ( cluster size varies from 4 to 8). With the help of experimental results we have analyzed the alteration in the MFPGA area with different LUT and cluster sizes. We have shown that in general LUTs having 4 or 5 inputs and clusters having 4 or 5 LUTs per cluster produce most efficient results in terms of area for the tree based architecture. We have also determined the mutation in the number of switches crossed by the critical path with changing LUT and cluster size and we have shown that architectures with higher LUT size and higher cluster size can be more optimal in terms of critical path though they are not optimal in terms of area.
Starting Page	115
Ending Page	120
File Size	600207
Page Count	6
File Format	PDF
ISBN	9781424437481
DOI	10.1109/ReConFig.2008.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-03
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Genetic mutations Computer architecture Switches Table lookup Field programmable gate arrays CAD tools FPGA design
Content Type	Text
Resource Type	Article

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