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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Farooq, U. Parvez, H. Amouri, E. Mehrez, H. Marrakchi, Z. |
| Copyright Year | 2011 |
| Description | Author affiliation: FLEXRAS Technologies, Paris, France (Marrakchi, Z.) || LIP6, UPMC Paris, France (Farooq, U.; Parvez, H.; Amouri, E.; Mehrez, H.) |
| Abstract | An application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density. An ASIF is reduced from an FPGA for a predefined set of applications that operate at mutually exclusive times. This work presents a new tree-based ASIF and uses a set of 16 MCNC benchmarks to explore the effect of lookup table (LUT) and arity size on it and results are then compared with those of mesh-based ASIF. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results but poor performance results. Finally experimental results show that LUT 4 with arity 16 gives best area-delay product and compared to mesh-based ASIF, this combination gives 12% routing area gain. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 2409690 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612848990 |
| e-ISBN | 9781612849003 |
| DOI | 10.1109/DTIS.2011.5941426 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-04-06 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Routing Table lookup Partitioning algorithms Field programmable gate arrays Optimization |
| Content Type | Text |
| Resource Type | Article |
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