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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jae-Sik Lee Kwyro Lee Song Bai Park |
| Copyright Year | 1991 |
| Description | Author affiliation: Central Res. Lab., GoldStar Electron Co. Ltd., Seoul, South Korea (Jae-Sik Lee) |
| Abstract | A new high resolution A/D converter architecture based on digital prediction and analog correction is proposed. Current input is estimated digitally using past history and converted to analog using low resolution DAC. The error signal between the input and predicted signal voltages is converted to digital using flash sub-ADC with smaller resolution. The correct digital signal is then obtained by adding the error to the predicted digital signal. The functionality of the architecture has been confirmed by a bread board circuit using commercially available ADC and DAC and a logic circuit designed using EPLD. This new architecture is suitable for high resolution ADC at medium speed. The specific example of 10 bit ADC with a 6 bit subconverter using third order polynomial extrapolation works successfully at 15 times Nyquist rate, compared to the theoretical rate of 10 times.<> |
| Starting Page | 560 |
| Ending Page | 563 |
| File Size | 264674 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/CICCAS.1991.184416 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-06-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Extrapolation Laboratories Signal processing Analog circuits Polynomials History Analog-digital conversion Signal resolution Digital circuits Electrons |
| Content Type | Text |
| Resource Type | Article |
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