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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Li, D.K.C. Chen, R.M.M. |
| Copyright Year | 1991 |
| Description | Author affiliation: City Polytech. of Hong Kong, Hong Kong (Li, D.K.C.; Chen, R.M.M.) |
| Abstract | Most algorithms using an analytical approach for tolerance analysis and yield maximization are based on certain assumptions which may not be true in practical design problems. Thus Monte Carlo analysis is required to be carried out in order to give a more precise estimation of the yield. In this paper, the problem of nominal design and tolerance assignment is formulated as an optimization problem, in which many SPICE runs are required for the estimation of circuit product yields. Two levels of parallelism are identified. Transputers are chosen as the hardware platform for the implementation of the proposed parallel processing technique to speed up the computation.<> |
| Starting Page | 761 |
| Ending Page | 764 |
| File Size | 316287 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/CICCAS.1991.184471 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-06-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Concurrent computing Monte Carlo methods Circuits Tolerance analysis Parallel processing SPICE Hardware Yield estimation Design optimization |
| Content Type | Text |
| Resource Type | Article |
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