NDLI: Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC

Content Provider	IEEE Xplore Digital Library
Author	Mingwen Zhang Yongsheng Yin Honghui Deng Hongmei Chen
Copyright Year	2012
Description	Author affiliation: Institute of VLSI Design, Hefei University of Technology, Hefei, China (Mingwen Zhang; Yongsheng Yin; Honghui Deng; Hongmei Chen)
Abstract	This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.
Starting Page	1
Ending Page	5
File Size	309476
Page Count	5
File Format	PDF
ISBN	9781467321440
ISSN	21635048
e-ISBN	9781467321457
e-ISBN	9781467321433
DOI	10.1109/ICASID.2012.6325310
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Operational amplifiers high-performance pipelined ADC Image edge detection Noise 50% duty cycle nonoverlapping clock Jitter the duty cycle detector clock jitter Voltage control Delay Clocks
Content Type	Text
Resource Type	Article

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