NDLI: A multi-phase clock design for super high-speed time interleaved analog-to-digital converter

Content Provider	IEEE Xplore Digital Library
Author	Yu-Han Gao Yong-Lu Wang Zheng-Ping Zhang
Copyright Year	2012
Description	Author affiliation: The NO.24th institute of CETC, Chongqing 400060, China (Yu-Han Gao; Yong-Lu Wang; Zheng-Ping Zhang)
Abstract	In this paper, we present a multi-phase clock (MPC) which is used in a super high-speed time interleaved analog-to-digital converter (TI ADC). To meet the timing requirements of the whole ADC, timing design between channels must be performed carefully, meanwhile, because the signal-to-noise ratio(SNR) of the whole ADC is restrained to the time-skew and jitter performance of the multi-phase clock, lower these timing errors is very important for TI ADC. We use a shift register based multi-phase generator to implement the multiphase relationship between sub-clocks. Digital calibration of the time-skew of single channel clock and serial peripheral interface (SPI) are adopted to lower timing errors between them further more. As a demonstration, a 4-phase clock is implemented, the presented clock circuit is used in a 8bit 5Gsps TI ADC. The whole TI ADC is implemented using a 0.18μm SiGe BiCMOS process. As a result of test, the whole ADC has a SNR of about 45dB at the input frequency of 495MHZ.
Starting Page	1
Ending Page	4
File Size	341044
Page Count	4
File Format	PDF
ISBN	9781467321440
ISSN	21635048
e-ISBN	9781467321457
e-ISBN	9781467321433
DOI	10.1109/ICASID.2012.6325291
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing jitter multi-phase clock time-skew Shift registers Calibration SPI jitter super high-speed SNR Timing TI ADC Clocks Signal to noise ratio
Content Type	Text
Resource Type	Article

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