NDLI: An FPGA implementation of a simple lossless data compression coprocessor

Content Provider	IEEE Xplore Digital Library
Author	Langi, A.Z.R.
Copyright Year	2011
Description	Author affiliation: ITB Research Center on Information and Communication Technology, Institut Teknologi Bandung, JalanGaneca 10, Indonesia 40132 (Langi, A.Z.R.)
Abstract	The paper describes a Field Programmable Gate Array (FPGA)-based lossless data compression coprocessor using implementing a compression method developed by Rice. We have implemented the Rice code (both encoder and decoder) for 8 bit/sample data on an FPGA Xilinx XC4005. The code has been designed to be optimal on 1.5 < H < 7.5 bits/sample, that is usually required in lossless image compression. The encoder and decoder can achieve 11.6 MHz and 19.4 MHz clock, respectively, where a 10 MHz clock corresponds to a 1.5 Mbits/s throughput. The XC4005 contains combinatorial logic units (CLU) and I/O pins. The Rice encoder uses 30% CLB F&G, 15% CLB H, 16% CLB FF, and 34% I/O pins. The Rice decoder uses 31% CLB F&G, 19% CLB H, 16% CLB FF, and 34% I/O pin. Hence, an X4005 is sufficient to implement both encoder and decoder.
Starting Page	1
Ending Page	4
File Size	815341
Page Count	4
File Format	PDF
ISBN	9781457707537
ISSN	21556830
e-ISBN	9781457707520
DOI	10.1109/ICEEI.2011.6021669
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-17
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image coding FPGA Implementation Radiation detectors Lossless Compression Decoding Pins Synchronization Rice coder Field programmable gate arrays Coprocessors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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