NDLI: Performance study of 1 bit static RAM based on process technologies

Content Provider	IEEE Xplore Digital Library
Author	Tumiran, N. Awan, M.
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, 31750, Tronoh, Perak Darul Ridzuan, Malaysia (Tumiran, N.; Awan, M.)
Abstract	A basic memory cell of SRAM topology consists of four transistors which act as a flip flop and two more transistors will act as pass transistor. In this study, experiment is done by varying the values of different variables that can affect the performance of basic memory cell. Among the variables are magnitudes of voltage supply, temperature, clock frequency and process technology used in fabrication of memory cell. These variables will have their own limit due to the configuration of circuit and properties transistor parameters in the memory cell. These values will determine the performance of the memory cell. The studies are carried out using various process technologies by simulation at schematic level. The results show that higher clock frequency will require higher value of supplied voltage. Lower supplied voltage will make SRAM failed to operate at high temperature. Different process technology will also influence value for minimum supplied voltage used and range temperature that the SRAM circuit can operate properly. The process technology of hp14tb has the minimum supply voltage of 0.83 V at 5 MHz while ami16 has the widest effective range temperature from −229°C to 224°C at 100MHz and 1.3 V simulation.
Starting Page	1
Ending Page	5
File Size	738834
Page Count	5
File Format	PDF
ISBN	9781457707537
ISSN	21556830
e-ISBN	9781457707520
DOI	10.1109/ICEEI.2011.6021524
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-17
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Temperature distribution CMOS Random access memory process technology and clock frequency temperature Software Transistors Integrated circuit modeling SRAM Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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