NDLI: Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation

Content Provider	IEEE Xplore Digital Library
Author	Jabbar, M.H. Houzet, D. Hammami, O.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Eng., UTHM, Parit Raja, Malaysia (Jabbar, M.H.) \|\| GIPSA-Lab., St. Martin d'Hères, France (Houzet, D.) \|\| ENSTA Paristech, Palaiseau, France (Hammami, O.)
Abstract	3D integration is one of the feasible technologies for producing advanced computing architecture to support ever-increasing demand of higher performance computing especially in mobile devices. The emerging trend of multiprocessor architecture has made Network on Chip (NoC) architecture the best solution for future manycore architecture devices. In this work, we explore the implementation of heterogeneous 3D Multiprocessor System on Chip (MPSoC) stacking architecture and evaluate its performance in terms of timing and power consumption compared with its 2D counterpart. The proposed heterogeneous 3D MPSoC implementation approach is considered to be the best solution for the time being as there are no 3D-aware EDA tools available in the markets that capable of performing 3D optimization as in 2D EDA tools. We also perform physical implementation analysis on the clock tree structure between 2D and 3D architecture and examine the impact of using 2D EDA tools for designing 3D architecture. The implementation is based on industry-specific Tezzaron 3D IC technology and the evaluation is based on the GDSII results from physical design implementations.
Starting Page	127
Ending Page	135
File Size	1747508
Page Count	9
File Format	PDF
e-ISBN	9781479913145
DOI	10.1109/ASQED.2013.6643575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-26
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heterogeneous stacking Three-dimensional displays Program processors Multicore processing NoC Stacking MPSoC 3D IC Synchronization Clocks Physical design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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