NDLI: An electrical study of differential clock die-to-die interconnection in multi-chip packages

Content Provider	IEEE Xplore Digital Library
Author	Tang Min Keen Tan Wei Jern
Copyright Year	2013
Description	Author affiliation: Chipset & SOC Group, Intel Corp., Nibong Tebal, Malaysia (Tang Min Keen; Tan Wei Jern)
Abstract	This paper presents an electrical study on die-to-die interconnect, differential clock signals in MCPs. The paper seeks to tackle the issues caused by shorter and denser interconnection in combination with an ever-decreasing z-height profile. The proposed methods focus on buffer and channel design on existing or new signaling. Of note, they maintain a fair amount of design flexibility, while not jeopardizing overall margins. The methods primarily mitigate harmful ringing, ledge effects and excessively slow slew rates in the monotonic region in both MCP and discrete solutions. Ultimately, this translates into a shift in line with recent platforms' sleek and thin form factor and in turn, a cost saving benefit.
Starting Page	196
Ending Page	199
File Size	775265
Page Count	4
File Format	PDF
e-ISBN	9781479913145
DOI	10.1109/ASQED.2013.6643587
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-26
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power transmission lines die-to-die interconnection ledges and ringing mitigation Crosstalk Capacitance Reflection Impedance Microstrip buffer design Clocks channel margin improvement
Content Type	Text
Resource Type	Article

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