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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Arreghini, A. Van den bosch, G. Kar, G.S. Van Houdt, J. |
| Copyright Year | 2012 |
| Abstract | We present a thorough investigation of scalability perspectives of 3D SONOS devices through simulations calibrated on cylindrical test structures. We identify the key technological challenge limiting the scalability of this solution and found that, even with the present limitations, 3D SONOS arrays could achieve bit density 3-4 generations ahead of the current planar Floating-Gate technology. Moreover, because of the more demanding constraints, MLC operations will not provide clear benefits over SLC in this technology |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 307262 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467310796 |
| e-ISBN | 9781467310819 |
| DOI | 10.1109/IMW.2012.6213682 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-20 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | SONOS devices Performance evaluation Microprocessors Computer architecture Logic gates Three dimensional displays Argon |
| Content Type | Text |
| Resource Type | Article |
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