NDLI: A synchronous DRAM controller for an H.264/AVC encoder

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Volume 01 - 2008

A synchronous DRAM controller for an H.264/AVC encoder

Content Provider	IEEE Xplore Digital Library
Author	Gyounghwan Hyun Yongseok Jin Jinsu Jung Seongyoon Kim Hyuk-Jae Lee
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul (Gyounghwan Hyun; Yongseok Jin; Jinsu Jung; Seongyoon Kim; Hyuk-Jae Lee)
Abstract	In order to use a synchronous dynamic RAM (SDRAM) as the off-chip memory of an H.264/AVC encoder, this paper proposes an efficient SDRAM memory controller with an asynchronous bridge. With the proposed architecture, the SDRAM bandwidth is increased by making the operation frequency of an external SDRAM higher than that of the hardware accelerators of an H.264/AVC encoder. Experimental results show that the encoding speed is increased by 30.5% when the SDRAM clock frequency is increased from 100 MHz to 200 MHz while the H.264/AVC hardware accelerators operate at 100 MHz.
File Size	113273
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815697
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Encoding SDRAM controller Bridges H.264/AVC encoder Bandwidth Frequency DRAM chips Automatic voltage control Hardware Asynchronous bridge SDRAM Clocks
Content Type	Text
Resource Type	Article

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