NDLI: A 5-Gb/s continuous-time adaptive equalizer and CDR using 0.18μm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Tae-Ho Kim Sang-Ho Kim Jin-Ku Kang
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., INHA Univ., Incheon (Tae-Ho Kim; Sang-Ho Kim; Jin-Ku Kang)
Abstract	In this paper, a 5-Gb/s receiver with adaptive equalizer and clock and data recovery(CDR) for serial link interface is proposed. In order to operate adaptively at 5-Gb/s data rate, LMS algorithm uses two internal signals from slicers which does not have an effect on gain boosting performance. In addition, this scheme enables it to operate without passive filter since two internal signals of slicers has a similar DC magnitude. The proposed adaptive equalizer in this receiver can compensate up to 20-dB and operate in various environments, which are 15-m shield twisted pair(STP) cable for DisplayPort and flame retardant 4(FR-4) traces up to 60-inch adaptively. This work is implemented 0.18-mum 1-poly 4-metal CMOS technology. Power dissipation of the equalizer is only 6-mW and it occupies 200 mum times 350 mum. Total power dissipation of the combined CDR is 164-mW (including output buffers) and operating range is available up to 5-Gb/s.
File Size	1089630
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815681
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Passive filters FFE Backplane Adaptive equalizers Performance gain Flame retardants Boosting Receiver Least squares approximation Cable shielding CDR DisplayPort CMOS technology Power dissipation Clocks Adaptive equalizer
Content Type	Text
Resource Type	Article

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