NDLI: Selective multiplexer-removal algorithm for lowering power consumption of circuits

Content Provider	IEEE Xplore Digital Library
Author	Chi-Hoon Shin Myeong-Hoon Oh Young-Woo Kim Sung-Nam Kim Seong-Woon Kim
Copyright Year	2008
Description	Author affiliation: Electron. & Telecommun. Res. Inst., Daejeon (Myeong-Hoon Oh; Young-Woo Kim; Sung-Nam Kim; Seong-Woon Kim) \|\| Comput. Software & Eng., Univ. of Sci. & Technol. (UST), Daejeon (Chi-Hoon Shin)
Abstract	In this paper we propose an algorithm about aggressive, but partial removal of multiplexers used for sharing functional units (FUs). By eliminating some multiplexers and duplicating the FU related, the proposed algorithm could be more advantageous for low power circuits than just keeping the multiplexers. To determine whether a removal of a group of multiplexers is beneficial or not, we compared a FU with multiplexers to multiple replications of the FU without any multiplexer under various conditions. Through the experiments, we aggregated information to be used for finding appropriate multiplexers to be extricated from circuit netlist; using the information, we built an automated algorithm to remove particular multiplexers; we applied it to a netlist of 16 bit processor. The processor that is newly generated by the algorithm consumed average about 12% less power than the initial processor.
File Size	144541
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815690
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Energy consumption Costs Design automation Design methodology Software algorithms Logic design Telecommunication computing design automation Power engineering computing multiplexer Logic circuits low power
Content Type	Text
Resource Type	Article

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