NDLI: Digital power estimation flow combining academic and industrial tools

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Volume 02 - 2008

A new design method to reduce the power consumption in a flash-A/D converter

Spread spectrum clock generator for DisplayPort

A design guide for 3-stage CMOS nested Gm-C operational amplifier with area or current minimization

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort

A CMOS linear preamplifier design for electret microphones

A study of detection algorithm for DAA regulation of Korea using MB-OFDM UWB receiver

Implementation of FlexRay protocol with an automotive application

New sum-product algorithm using approximation method for low complexity LDPC decoding

Efficient CTC interleaver and deinterleaver for the WiMAX standard

Low complexity soft-decision demapper for high order modulation of DVB-S2 system

Implementation of DCT based OFDM system

A design of DisplayPort link layer

A 5-Gb/s continuous-time adaptive equalizer and CDR using 0.18μm CMOS

Software implementation of TPEG decoder on a T-DMB using X-PAD

Design of application specific processor for H.264 inverse transform and quantization

Design and implementation of 16-bit fixed point digital signal processor

Multiplier design based on ancient Indian Vedic Mathematics

Design of high energy efficiency 32bit processing unit using instruction-levels data gating and dynamic voltage scaling techniques

A new scheduling technique based on Dynamic Voltage Scaling for MPSoC

Low-power dynamic scheduling algorithm For real-time multiprocessor systems

Novel dynamic power management technique for multi-core based mobile devices

Selective multiplexer-removal algorithm for lowering power consumption of circuits

Digital power estimation flow combining academic and industrial tools

Enhanced parallel decoding for H.264/AVC CAVLC by using precomputation

Implementation of 3D graphics accelerator using full pipeline scheme on FPGA

Hardware implementation of motion estimation using a sub-sampled block for frame rate up-conversion

Design of voice guiding system using serial connection technique of speakers

Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files

A synchronous DRAM controller for an H.264/AVC encoder

Simplified NAL decoder for H.264/AVC baseline profile

Image quality enhancement by real-time gamma correction for a CMOS image sensor in mobile phones

An efficient color demosaicing using Approximated Directional Line Averages

A unified transform unit for H.264

The compensation system for the event in the fuel cell mobile phone

Wideband LPF for WiMedia UWB RF transceiver

A 1.2V 3 ∼ 8 GHz low noise amplifier in 0.13μm CMOS

RF receiver chip set employing 0.13 μm CMOS technology for application to K-band commercial automotive radar system

A Linear wideband CMOS LNA for 3–5 GHZ UWB systems

Discontinuous RC interconnect line analysis for accurate timing determination

Crosstalk avoidance method considering multi-aggressors

Performance analysis of NoC structure based on Star-Mesh Topology

Power supply noise reduction by clock scheduling with gate-level current waveform estimation

Star-Mesh NoC based multi-channel H.264 decoder design

The use of Fair Y-Sim for optimizing mapping set selection in hardware/software co-design

A design verification kit for passive RFID system on a Chip

Leveraging CMOS design tools for QCA designs

Assessment of using the statistical timing analysis software for the VLSI design at the macro level

Operation about multiple scan chains based on system-on-chip

A programmable memory BIST for embedded memory

Path delay fault diagnosis using path scoring

Volume 01 - 2008

Digital power estimation flow combining academic and industrial tools

Content Provider	IEEE Xplore Digital Library
Author	Mehrotra, R. English, T. Man, K.L. Popovici, E. Schellekens, M.P.
Copyright Year	2008
Description	Author affiliation: Dept. of Microelectron. Eng., Univ. Coll. Cork (UCC), Cork (Mehrotra, R.; English, T.; Man, K.L.; Popovici, E.; Schellekens, M.P.)
Abstract	We analyse how a power estimation and optimisation design flow from the academic domain may be integrated into an industrial design flow and how this integration creates an open-source environment in which new techniques can be developed and compared. In this integrated design flow, new tools are introduced and several practical issues such as technology libraries and the use of simulation data to derive realistic power estimation results are addressed. Experimental results (enabling power saving of over 40%) demonstrate the applicability and effectiveness of the integration of the two design flows. The integrated design flow provides a solid platform for future research in logic synthesis, power estimation and power optimisation.
File Size	222309
File Format	PDF
ISBN	9781424425983
DOI	10.1109/SOCDC.2008.4815691
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing Electronic design automation and methodology Logic programming Solids Logic design Libraries Hardware design languages Logic testing Open source software Design optimization
Content Type	Text
Resource Type	Article

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