NDLI: Design and Implementation of Memory Pools for Embedded DSP

Content Provider	IEEE Xplore Digital Library
Author	Xi-min Wang Zhe Wang
Copyright Year	2008
Description	Author affiliation: Naval Univ. of Eng., Wuhan (Xi-min Wang; Zhe Wang)
Abstract	Two sorts of pool memory are developed for the needs of programming reconfigurable embedded DSP applications. One-piece signal free list and first-fit police are used in the designed of equal size memory pool in which the search time of a free block is faster than c-runtime allocator. Based on two-level segregated fit algorithm, unequal size memory pool is implemented for the requirements of low fragmentation and bounded responded times. The boundary of memory block allocated can be four words aligned. For making the allocation polices adaptable to various DSP hardware resource and DSP applications, a reusable software framework used for management of memory pools is presented. Pattern and bridge design pattern are used in the designing of frame strategy work. The memory allocation algorithm can be selected according to DSP application and DSP memory resources. As a result, DSP embedded system developers can create multiple allocators for a signal complex application. The software framework and the algorithm are applied for ADTS101 DSP hardware platform.
Starting Page	160
Ending Page	164
File Size	292848
Page Count	5
File Format	PDF
ISBN	9780769533360
DOI	10.1109/CSSE.2008.1273
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	dynamic memory allocator Software algorithms DSP application Application software memory pool design pattern Bridges Memory management Embedded system Digital signal processing Hardware Resource management Software reusability Signal design real-time operating system
Content Type	Text
Resource Type	Article

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