NDLI: Performance Pattern of Unified Parallel C on Multi-core Clusters

Content Provider	IEEE Xplore Digital Library
Author	Hamid, N.A.W.A. Serres, O. Anbar, A. Hassan, S.
Copyright Year	2013
Description	Author affiliation: Fac. of Comput. Sci. & Inf. Technol., Univ. Putra Malaysia, Serdang, Malaysia (Hassan, S.) \|\| Dept. of Electr. & Comput. Eng., George Washington Univ., Washington, DC, USA (Hamid, N.A.W.A.; Serres, O.; Anbar, A.)
Abstract	The Partitioned Global Address Space (PGAS) model has been widely used in multi-core clusters as an alternative to MPI. Among the widespread use is Unified Parallel C (UPC). Previous research has shown that UPC performance is comparable with MPI, however in certain cases UPC require hand-tuning techniques such as prefetching and privatized pointers-to-shared to improve the performance. In this paper we reviews, evaluate and analyze the performance pattern between UPC Naïve, UPC optimize and MPI on two different multi-core clusters architecture. We focus our study using matrix multiplication as the benchmark and perform our experimental on two distributed memory machine, Cray XE6 with Gemini interconnects and Sun Cluster with Infiniband interconnects. We provide analysis on each core execution time to understand the pattern of communication for both machines. We also demonstrate the gaps between naïve and optimized are depends on the compiler with its associate distributed memory machine. We also observed unnecessary optimization for certain programs related to HPC architecture and compiler.
Sponsorship	IEEE Comput. Soc.
Starting Page	1751
Ending Page	1757
File Size	649261
Page Count	7
File Format	PDF
ISBN	9780769550886
DOI	10.1109/HPCC.and.EUC.2013.250
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-13
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Performance Evaluation Random access memory Computer architecture MPI Benchmark testing UPC PGAS Sun Optimization Electronics packaging Gemini
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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