NDLI: A FPGA-Based High Performance Acceleration Platform for the Next Generation Long Read Mapping

Content Provider	IEEE Xplore Digital Library
Author	Peng Chen Chao Wang Xi Li Xuehai Zhou
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Sci. & Technol. of China, Hefei, China (Peng Chen; Chao Wang; Xi Li; Xuehai Zhou)
Abstract	To compare the newly determined sequences against the subject sequences stored in the databases is a critical job in the bioinformatics. Fortunately, recent survey reports that the state-of-the-art aligners are already fast enough to handle the ultra amount of short sequence reads in the reasonable time. However, for aligning the long sequence reads (> 400 bp) generated by the next generation sequencing (NGS) technology, it is still quite inefficient with present aligners. Furthermore, the challenge becomes more and more serious as the lengths and the amounts of the sequence reads are both keeping increasing with the improvement of the sequencing technology. Thus, it is extremely urgent for the researchers to enhance the performance of the long read alignment. In this paper, we propose a novel FPGA-based system to improve the efficiency of the long read mapping. Compared to the state-of-the-art long read aligner BWA-SW, our accelerating platform could achieve better performance. Experiments demonstrate that for reads with lengths ranging from 512 base pairs up to 4096 base pairs, the described system obtains a 10×-48× speedup for the bottleneck of the software. As to the complete mapping procedure, the FPGA-based platform could achieve a 1.9×-3.2× speedup versus the BWA-SW aligner, reducing the alignment cycles from weeks to days.
Sponsorship	IEEE Comput. Soc.
Starting Page	308
Ending Page	315
File Size	560168
Page Count	8
File Format	PDF
ISBN	9780769550886
DOI	10.1109/HPCC.and.EUC.2013.52
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-13
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential analysis Microprocessors Genomics Computer architecture Sequence alignment Software Smith-Waterman Acceleration long read mapping Bioinformatics BWA-SW hardware acceleration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Accelerating the Next Generation Long Read Mapping with the FPGA-Based System

Accelerating the next generation long read mapping with the FPGA-based system

Acceleration of the long read mapping on a PC-FPGA architecture (abstract only)

Optimization Strategies for Smith-Waterman Algorithm on FPGA Platform

BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman aligner

A Novel High-Throughput Acceleration Engine for Read Alignment

Hardware acceleration of sequence alignment algorithms-an overview

Next-generation massively parallel short-read mapping on FPGAs

A comparative analysis of smith-waterman based partial alignment

A FPGA-Based High Performance Acceleration Platform for the Next Generation Long Read Mapping

Similar Documents

Accelerating the Next Generation Long Read Mapping with the FPGA-Based System

Accelerating the next generation long read mapping with the FPGA-based system

Acceleration of the long read mapping on a PC-FPGA architecture (abstract only)

Optimization Strategies for Smith-Waterman Algorithm on FPGA Platform

BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman aligner

A Novel High-Throughput Acceleration Engine for Read Alignment

Hardware acceleration of sequence alignment algorithms-an overview

Next-generation massively parallel short-read mapping on FPGAs

A comparative analysis of smith-waterman based partial alignment

A FPGA-Based High Performance Acceleration Platform for the Next Generation Long Read Mapping