NDLI: An efficient implementation method of parallel processing Viterbi decoders for UWB systems

Content Provider	IEEE Xplore Digital Library
Author	Seongjoo Lee
Copyright Year	2009
Description	Author affiliation: Department of Information and Communication Eng., Sejong University, 98 Gunja-Dong, Gwangjin-Gu, Seoul, 143-747, Republic of Korea (Seongjoo Lee)
Abstract	In this paper, we present an efficient implementation method for parallel processing Viterbi decoders in UWB systems. In our method, we use an automatic HDL code generator designed by high level languages (C or C++) to produce the synthesizable HDL code for a parallel processing Viterbi decoder automatically depending on the hardware architecture for parallel processing as well as parameters for channel coding, which makes it easy to find the optimum architecture under the specified working speed and CMOS technology. We apply the proposed method to the design of Viterbi decoders for UWB systems, in which it is an important issue to find the optimum architecture working at the speed of 132MHz in 4-way parallel processing. From the results, we can find that our scheme can produce all the possible architectures of Viterbi decoder properly without manual efforts and that the Viterbi decoder with $radix-4^{2}$ ACS structure has the lowest hardware costs working at the required clock speed under 0.13um CMOS technology.
Starting Page	512
Ending Page	515
File Size	368629
Page Count	4
File Format	PDF
ISBN	9781424433872
DOI	10.1109/ECTICON.2009.5137060
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-06
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Viterbi algorithm Design methodology Manuals Parallel processing CMOS technology CMOS process Decoding Hardware design languages High level languages Channel coding
Content Type	Text
Resource Type	Article

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