NDLI: High-speed VLSI architectures for Huffman and Viterbi decoders

Content Provider	IEEE Xplore Digital Library
Author	Parhi, K.K.
Copyright Year	1992
Abstract	Pipelined and parallel architectures for high-speed implementation of Huffman and Viterbi decoders (both of which belong to the class of tree-based decoders) are presented. Huffman decoders are used for lossless compression. The Viterbi decoder is commonly used in communications systems. The achievable speed in these decoders is inherently limited due to the sequential nature of their computation. This speed limitation is overcome using a previously proposed technique of look-ahead computation. The incremental computation technique is used to obtain efficient parallel (or block) implementations. The decomposition technique is exploited to reduce the hardware complexity in pipelined Viterbi decoders, but not in Huffman decoders. Logic minimization is used to reduce the hardware overhead complexity in pipelined Huffman decoders.<>
Sponsorship	IEEE Circuits and Systems Society
Starting Page	385
Ending Page	391
Page Count	7
File Size	414790
File Format	PDF
ISSN	10577130
Volume Number	39
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-06-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Viterbi algorithm Decoding Automata Pipeline processing Hardware Image coding Speech Parallel architectures Concurrent computing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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