NDLI: Exploring the optimum buffer size of an emerging stream cipher engine

Content Provider	IEEE Xplore Digital Library
Author	Fukase, M.-a. Ohsumi, Y. Sato, T.
Copyright Year	2009
Description	Author affiliation: Graduate School of Science and Technology, Hirosaki University, Japan (Fukase, M.-a.; Ohsumi, Y.) \|\| Computer and Network Systems Center, Hirosaki University, Japan (Sato, T.)
Abstract	One of crucial points for ubiquitous network is to keep the temporary security without relying on permanent network infrastructure. Considering a practical solution of ubiquitous security is a safety aware, high-performed single chip processor, we have exploited a multimedia stream cipher engine and its VLSI chip implementation. In order to keep security, usability, speed, and power consciousness, the stream cipher engine takes a compact multicore architecture. Each core implements a double cipher scheme that covers RAC (random addressing cryptography) and data sealing. The double cipher is microarchitecture-based, software-transparent hardware cryptography that offers the protection of the whole data with negligible hardware cost and moderate performance overhead. We studied in previous works the chip implementation of the stream cipher engine by using 0.18-µm standard cell CMOS technologies. Prospective specifications of chips were also examined by means of rough evaluation. This paper focuses on the latest version of the stream cipher engine chip and evaluates more in detail power dissipation, clock speed, running time, and throughput by using Synopsys Design Compiler. From the cipher streaming buffer size dependency of these specificative factors, we make clear the tradeoff between them and achieve the guideline of optimum buffer size in view of safety and performance for ubiquitous computing.
Starting Page	607
Ending Page	610
File Size	1523667
Page Count	4
File Format	PDF
ISBN	9781424433872
DOI	10.1109/ECTICON.2009.5137080
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-06
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Data security Very large scale integration SIMD hardware cryptography processor Engines streaming Streaming media CMOS technology Hardware Safety Cryptography Ubiquitous security Usability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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