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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Alvarez, R. Lizama, I. Bernet, S. |
| Copyright Year | 2014 |
| Description | Author affiliation: Power Electron. Lab., Tech. Univ. Dresden, Dresden, Germany (Alvarez, R.; Lizama, I.; Bernet, S.) |
| Abstract | The increasing demand for large power ratings and the physically limited maximum current density of semiconductor devices in power electronics make the connection of semiconductors in parallel or series an interesting alternative for high power applications. The selection of the devices, the manual parametrization of gate units and the substantial device de-rating are important disadvantages of state of the art converters with parallel connected IGBTs. A new, low expensive and automated delay time compensation method without additional current measurements was introduced in the ECCE 2011. This paper reviews the structure and function of this new scheme and presents details of the implementation challenges for this solution. Furthermore, it shows the extension of the scheme for n parallel connected IGBTs or other semiconductors. It also experimentally investigates the performance of the implemented algorithm and its issues in a 690V converter with three parallel connected IGBTs. |
| Starting Page | 1 |
| Ending Page | 10 |
| File Size | 2051081 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781479930159 |
| DOI | 10.1109/EPE.2014.6910897 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-08-26 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Insulated gate bipolar transistors Voltage measurement Current measurement Switches Delays Registers |
| Content Type | Text |
| Resource Type | Article |
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