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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Le Kang Yici Cai Jin Shi Xianlong Hong |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing (Le Kang; Yici Cai; Jin Shi; Xianlong Hong) |
| Abstract | In this paper, in-depth experimental study was conducted on random walk approach for DC analysis of P/G network, and we also extended the random walk approach for RLC networks by Norton companion without any adjustment for the algorithm. Our experimental results suggest that the CPU times of solving several nodes by the algorithm is about one order of magnitude speedup over PCG, and the speedup may be higher if the circuits contain more VDD nodes. We also show how accuracy-runtime tradeoff of random walk algorithm could be made through adjusting the parameters of the algorithm. Our extended method works pretty well on both DC analysis and transient analysis comparing with direct method |
| Sponsorship | IEEE Circuits and Syst. Soc. HKUST UESTC City Univ. of Hong Kong |
| Starting Page | 2401 |
| Ending Page | 2405 |
| File Size | 5169840 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780395840 |
| DOI | 10.1109/ICCCAS.2006.285161 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-06-25 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Computer science Analytical models Circuit simulation RLC circuits Voltage Power grids Power system reliability Iterative methods Transient analysis |
| Content Type | Text |
| Resource Type | Article |
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