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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ling Yang Qiang Zhou Xianlong Hong |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing (Ling Yang; Qiang Zhou; Xianlong Hong) |
| Abstract | As technology moves into VDSM arena, the integration density of ICs goes higher and higher. It makes the congestion a global issue, for it appears in many pieces on the chip while not only in some bins. Many methods proposed before just focused on reducing the congestion restrictedly in one bin, but can not handle the problem of global congestion effectively. In this paper, a congestion-driven placement method using cell spreading is proposed, which alters the routing supply and the routing demand by row or column uniformly. During the spreading process, cells move along the direction in which the congestion is cut down. The average routing demands are set to control the extent for cell spreading to avoid producing new congestion. The experiments show that our method can reduce the congestion by 31.4% in x direction and 22.1% in y direction on average while within 5% wire length being increased |
| Sponsorship | IEEE Circuits and Syst. Soc. HKUST UESTC City Univ. of Hong Kong |
| Starting Page | 2415 |
| Ending Page | 2419 |
| File Size | 6350958 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780395840 |
| DOI | 10.1109/ICCCAS.2006.285164 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-06-25 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer science Very large scale integration Routing Topology Timing Partitioning algorithms Performance analysis Wire Quadratic programming Design optimization |
| Content Type | Text |
| Resource Type | Article |
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