NDLI: A novel low-power adiabatic SRAM with an energy-efficient line driver

Content Provider	IEEE Xplore Digital Library
Author	Jianping Hu Weiqiang Zhang Yinshui Xia
Copyright Year	2004
Description	Author affiliation: Fac. of Inf. Sci. & Technol., Ningbo Univ., China (Jianping Hu; Weiqiang Zhang)
Abstract	A novel 64/spl times/64 bit adiabatic SRAM is designed using 0.25 /spl mu/m CMOS technology. An adiabatic line driver, which does not have non-adiabatic loss on output loads through using feedback control from the next-stage buffer, is used to recover the charge of the large switching capacitance on the bit-lines and word-lines in a fully adiabatic manner. The power consumption of the proposed SRAM is significantly reduced because the energy transferred to the large capacitance buses is mostly recovered. The energy and functional simulations are performed using the net-list extracted from the layout. HSPICE simulation results indicate energy savings of 75% to 85%, as compared to the conventional CMOS implementation, for clock rates ranging from 25 to 200 MHz.
Sponsorship	Ministry of Educ. (MOE) of PR China City Univ. of Hong Kong K.C. Wong Educ. Found
Starting Page	1151
Ending Page	1155
File Size	296445
Page Count	5
File Format	PDF
ISBN	0780386477
DOI	10.1109/ICCCAS.2004.1346379
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy loss Energy consumption Random access memory Capacitance CMOS technology Energy efficiency Power dissipation Feedback control Clocks Driver circuits
Content Type	Text
Resource Type	Article

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