NDLI: Crosstalk minimization in four-layer non-Manhattan channel routing

Content Provider	IEEE Xplore Digital Library
Author	Yongbin Yu Bo Yang Xuliang Zhang Juebang Yu
Copyright Year	2004
Description	Author affiliation: Coll. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China (Yongbin Yu; Bo Yang; Xuliang Zhang; Juebang Yu)
Abstract	It's well known that a non-Manhattan channel router always uses no more tracks than a Manhattan channel router. For a bubble-sorting-based non-Manhattan channel, all of the nets can be routed by bubble-sorting swap passes in an optimal bubble-sorting solution, and these bubble-sorting swap passes can be further mapped onto track-to-track-routing processes in a 4-layer routing model. However, these proposed bubble-sorting-based non-Manhattan routers do not consider crosstalk or consider less, which has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits. In this paper, we study the problem of crosstalk minimization in a bubble-sorting based non-Manhattan channel. A rerouting algorithm that combines segment-rerouting technique and layer reassignment is presented. This algorithm can decrease the wire length and modify the layout so that the crosstalk in the channel is minimized. Experimental results show that the proposed approach can reduce the crosstalk by an average of 27.9 % on a set of benchmark examples.
Sponsorship	Ministry of Educ. (MOE) of PR China City Univ. of Hong Kong K.C. Wong Educ. Found
Starting Page	1281
Ending Page	1285
File Size	321506
Page Count	5
File Format	PDF
ISBN	0780386477
DOI	10.1109/ICCCAS.2004.1346407
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Geometry Heuristic algorithms Crosstalk Integrated circuit interconnections Very large scale integration Routing Minimization Educational institutions Wire Sorting
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Crosstalk minimization in three-layer HVH channel routing

Algorithms for high performance two-layer channel routing

Crosstalk minimization in two-layer channel routing

A graph theoretic approach to minimize total wire length in channel routing

High performance multilayer routing for VLSI circuit synthesis

Four layer wiring using adjacent-layer vias

A timing driven approach for crosstalk minimization in gridded channel routing

Minimum crosstalk channel routing with dogleg

Layer assignment problem for three-layer routing

Crosstalk minimization in four-layer non-Manhattan channel routing

Similar Documents

Crosstalk minimization in three-layer HVH channel routing

Algorithms for high performance two-layer channel routing

Crosstalk minimization in two-layer channel routing

A graph theoretic approach to minimize total wire length in channel routing

High performance multilayer routing for VLSI circuit synthesis

Four layer wiring using adjacent-layer vias

A timing driven approach for crosstalk minimization in gridded channel routing

Minimum crosstalk channel routing with dogleg

Layer assignment problem for three-layer routing

Crosstalk minimization in four-layer non-Manhattan channel routing