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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chengyi Xiong Sheng Zheng Jinwen Tian Jian Liu Chengyi Xiong |
| Copyright Year | 2004 |
| Description | Author affiliation: Key Lab. of Educ. Minist. for Image Process. & Intelligent Control, Huazhong Univ. of Sci. & Technol., Wuhan, China (Chengyi Xiong; Sheng Zheng; Jinwen Tian; Jian Liu) |
| Abstract | A novel VLSI architecture based on an improved lifting algorithm, which can be reconfigurable for 5/3 and 9/7 wavelet transforms, is proposed. The improved lifting algorithm, exploiting the parallelism of multiplication and addition operations based on the conventional lifting scheme, efficiently reduces the critical path delay. Systolic and the embedded pipeline techniques are adopted to optimize the design of the architecture, which significantly reduces the hardware complexity and power consumption of the design. Moreover, the proposed architecture works in a serial input fashion, with the result that the accessed memory needs only a single read port and a single write port, and can be easily extended to the implementation of a line-based architecture for 2D DWT. |
| Sponsorship | Ministry of Educ. (MOE) of PR China City Univ. of Hong Kong K.C. Wong Educ. Found |
| Starting Page | 728 |
| Ending Page | 732 |
| File Size | 255735 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780386477 |
| DOI | 10.1109/ICCCAS.2004.1346284 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-06-27 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wavelet transforms Energy consumption Filters Pipelines Very large scale integration Read-write memory Hardware Discrete wavelet transforms Delay Design optimization |
| Content Type | Text |
| Resource Type | Article |
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